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Gökçe Aydos

  • Fehlertoleranz für digitale Schaltungen
  • eingebettete Systeme mit Fokus auf FPGAs

Webseite: aydos.de

Fakultät Angewandte Informatik

Professor:innen

Professor

DEGG's 2.16

0991/3615-179

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Beitrag in Sammelwerk/Tagungsband

  • Gökçe Aydos
  • G. Fey

Exploiting error detection latency for parity-based soft error detection

pg. 3-8.

  • (2016)
Local triple modular redundancy (LTMR) is often the first choice to harden a flash-based FPGA application against soft errors in space. Unfortunately, LTMR leads to at least 300% area overhead. We propose a parity-based error detection approach, to use the limited resources of space-proven flash-based FPGAs more area-efficiently; this method can be the key for fitting the application onto the FPGA. A drawback of parity-based hardening is the significant impact on the critical path. To alleviate this error detection latency, pipeline structures in the design can be utilized. According to our results, this eliminates from 22% to 65% of the critical path overhead of the unpipelined error detection. Compared with LTMR, the new approach increases the critical path overhead of LTMR by a factor varying from 2 to 7.
  • Angewandte Informatik
  • DIGITAL
Beitrag in Sammelwerk/Tagungsband

  • Gökçe Aydos
  • G. Fey

In-circuit Error Detection with Software-based Error Correction - An Alternative to TMR

In: Formal Modeling and Verification of Cyber-Physical Systems. 1st International Summer School on Methods and Tools for the Design of Digital Systems, Bremen, Germany, September 2015 (Advanced lectures by leading scientists on cyber-physical systems modeling and verification) pg. 272-274.

  • (2015)
FPGAs are often utilized in space avionics. To protect the FPGA application data against radiation effects in space, data redundancy can be used. A well-known method is to triplicate the circuit and eliminate the erroneous circuit output with a local voter (TMR). Alternatively, in-circuit error detection with software-based error correction can be used, if the FPGA works as a co-module next to a processor running the mission software. In this work, we present an implementation of this method on a commonly used spacecraft data handling architecture.
  • Angewandte Informatik
  • DIGITAL

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