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Prof. Dr. Peter Faber

  • High Performance Computing (HPC)
  • Programmierung
  • Allgemeine GPU-Programmierung (GPGPU)

Professor

DEGG's 2.18

0991/3615-509


Sprechzeiten

Vgl. http://sprechstunde.peterfaber.net


Sortierung:
Vortrag

  • Peter Faber

Contactless Inductive Flow Tomography (CIFT) . Posterpräsentation

In: 6. Tag der Forschung

Technische Hochschule Deggendorf Deggendorf

  • 10.04.2019 (2019)
  • Elektrotechnik und Medientechnik
  • DIGITAL
Zeitschriftenartikel

  • Peter Faber
  • A. Größlinger

A Comparison of GPGPU Computing Frameworks on Embedded Systems

In: IFAC-PapersOnLine/13th IFAC and IEEE Conference on Programmable Devices and Embedded Systems — PDES 2015 vol. 48 pg. 240-245.

  • (2015)

DOI: 10.1016/j.ifacol.2015.07.040

Graphics processing units have found their way onto the die of embedded CPUs. Embedded devices have thus gained access to on-die parallel co-processors that can be put to good use with the help of the low-level OpenCL standard API, but also using programming frameworks that help making use of this additional compute power. This paper compares several programming frameworks with different coding styles. We report on the coding effort needed and the performance achieved on a Congatec conga-QG embedded computer on a module using two representative codes taken from the SHOC benchmark suite as comparison.
  • Elektrotechnik und Medientechnik
  • DIGITAL
Zeitschriftenartikel

  • Peter Faber
  • Sebastian Och
  • M. Schlott

Virtuelles Guckloch

In: c’t Magazin für Computer Technik vol. 24 pg. 212-216.

Heise

  • (2013)
  • Elektrotechnik und Medientechnik
Zeitschriftenartikel

  • M. Griebl
  • Peter Faber
  • C. Lengauer

Space-time mapping and tiling: a helpful combination

In: Concurrency and Computation: Practice and Experience vol. 16 pg. 221-246.

  • (2004)

DOI: 10.1002/cpe.772

Tiling is a well‐known technique for sequential compiler optimization, as well as for automatic program parallelization. However, in the context of parallelization, tiling should not be considered as a stand‐alone technique, but should be applied after a dedicated parallelization phase, in our case after space–time mapping. We show how tiling can benefit from space–time mapping, and we derive an algorithm for computing tiles which can minimize the number of communication startups, taking the number of physically available processors into account. We also present how the use of a simple cost model reduces real execution time.
  • Elektrotechnik und Medientechnik
Beitrag (Sammelband oder Tagungsband)

  • Peter Faber
  • M. Griebl
  • C. Lengauer

Polyhedral Loop Parallelization: The Fine Grain

In: Proceedings of the 11th Workshop on Compilers for Parallel Computers (CPC 2004). null (Research Report Series) pg. 25-36.

  • (2004)
  • Elektrotechnik und Medientechnik

Labore

DGS206 (HPC I / Computergrafik)


Vita

  • 2009 – jetzt: Professor (THD)
  • 2005 – 2009: Software-Engineer (science+computing ag)
  • 1999 – 2004: Wissenschaftlicher Mitarbeiter (Uni Passau)
  • 1998 – 1999: Wissenschaftlicher Mitarbeiter (GMD – Forschungszentrum Informationstechnik GmbH)